a. Field of the Invention
The present invention pertains to integrated circuit manufacturing and specifically to test samples used to qualify a new manufacturing process.
b. Description of the Background
In the development of a new manufacturing process for integrated circuits, certain design rules are created that define the capabilities of the process. A designer begins the design of new integrated circuits at the same time as the manufacturing capability is being developed. The concurrency of new process development and product design places great importance on the ability of the manufacturing process to be able to produce integrated circuits using those design rules.
The design rules include such things as minimum trace width, minimum distance between traces, the maximum number of vias that may be stacked on top of each other, and other such parameters. Typically, a manufacturer may guarantee that a process will manufacture good parts if the parts conform to the design rules, thus allowing the designers to begin integrated circuit designs many months before the manufacturing process is ready.
After the first production of a new integrated circuit design, there is generally a period of failure analysis as the design and manufacturing processes are adjusted to produce a successful product. The root cause failure analysis of some integrated circuits may be very time consuming, sometimes consuming days or even weeks to isolate a single fault on a single chip.
The failure analysis techniques available to development engineers include mechanical probing, optical beam induced current (OBIC), optical beam induced resistive change (OBIRCH), picosecond imaging circuit analysis (PICA), light induced voltage alterations (LIVA), charge induced voltage alterations (CIVA), various Scanning Electron Microscopy (SEM) techniques, active and passive voltage contrast, Electron Beam (E-Beam), and other techniques known in the art. In addition, destructive tests, such as etching and lapping, may be used to isolate and identify problems.
In many cases, the design of an integrated circuit may limit or prohibit certain techniques for ascertaining faults. For example, in order to probe a certain path using a laser technique, the path must not have another metal trace directly above the path of interest. Further, the various techniques may only isolate a problem within a certain section of the circuitry, but not to a specific trace or via.
E-Beam probing used in concert with active and passive voltage contrast techniques allow significant analysis of a board not typically available with other inspection techniques. With active voltage contrast the current electrical state of an integrated circuit wafer structure can be visibly ascertained. Whether a structure is at VDD, ground, or some indeterminate state is shown by the relative lightness or darkness of the appearance of the structure. Typically, grounded items appear dark, and items at VDD appear light. The dark and light appearance effect can be reversed if desired. Passive voltage contrast operates in a similar fashion, but there is no power applied to the circuit. The substrate is grounded, and the electrons from the SEM or E-Beam charge the ungrounded structures, while the grounded structures do not accept a charge. Passive voltage contrast techniques can be used during fabrication of a wafer to inspect each layer of the wafer as the layer is created, as well as after layers of a wafer have been polished off for closer inspection of obscured layers. The grounded structures typically appear dark while the ungrounded structures appear light. As with active voltage contrast, the darkness and lightness of grounded structures and ungrounded structures can be reversed if desired.
During process development and verification, it is important that faults are isolated to the exact location. For example, a via may have very high resistivity. In order for the manufacturing process to be corrected, the location of the via must be identified exactly. Failure analysis techniques that isolate only a section of an electric path are not sufficient for the fine tuning of the manufacturing process.